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1 ltc1875 1875f 15 m a quiescent current 1.5a monolithic synchronous step-down regulator portable computers portable instruments wireless modems , ltc and lt are registered trademarks of linear technology corporation. high efficiency step-down converter high efficiency: up to 95% low quiescent current: only 15 m a with no load 550khz constant frequency operation 2.65v to 6v input voltage range v out from 0.8v to v in , i out to 1.5a true pll frequency locking from 350khz to 750khz power good output voltage monitor low dropout operation: 100% duty cycle burst mode or pulse skipping operation current mode operation for excellent line and loadtransient response shutdown mode draws < 1 m a supply current 2% output voltage accuracy overcurrent and overtemperature protected available in 16-lead ssop package the ltc 1875 is a high efficiency 1.5a monolithic syn- chronous buck regulator using a constant frequency,current mode architecture. operating supply current is only 15 m a with no load and drops to < 1 m a in shutdown. the input supply voltage range of 2.65v to 6v makes theltc1875 ideally suited for single li-ion battery-powered applications. 100% duty cycle provides low dropout op- eration, extending battery life in portable systems. the switching frequency is internally set to 550khz, allow- ing the use of small surface mount inductors and capaci- tors. for noise sensitive applications, the ltc1875 can be externally synchronized from 350khz to 750khz. burst mode operation is inhibited during synchronization or when the sync/mode pin is pulled low. the internal synchronous switch increases efficiency and eliminates the need for an external schottky diode. low output voltages are easily supported with a 0.8v feedback reference voltage. the ltc1875 is available in a 16-lead ssop package. burst mode is a registered trademark of linear technology corporation. run/sssync/mode pgood i th pv in swp swn pgnd v fb sv in ltc1875 28.0k c in : taiyo yuden ceramic jmk325bj226mm c out : sanyo poscap 6tpa47m l1: toko 646cy-6r8m*v out connected to v in (minus switch and l1 voltage drop) for 2.65v < v in < 3.3v 1875 ta01 220pf 150k 88.7k c out 47 f v out * 3.3v l1 6.8 h sgnd 47pf c in 22 f v in 2.65v to 6v + efficiency vs output load current ouput current (ma) efficiency (%) 100 9590 85 80 75 70 65 60 55 0.1 10 100 1875 ta01a 1 1000 burst mode operationv out = 3.3v l = 6.8 h v in = 4.2v v in = 6v v in = 3.6v features descriptio u applicatio s u typical applicatio u downloaded from: http:///
2 ltc1875 1875f symbol parameter conditions min typ max units i vfb feedback current (note 4) 86 0 n a v fb regulated output voltage (note 4) 0 c t a 85 c 0.784 0.80 0.816 v (note 4) 40 c t a 85 c 0.740 0.80 0.840 v d v ovl overvoltage trip limit with respect to v fb d v ovl = v ovl ?v fb 20 60 110 mv d v uvl undervoltage trip limit with respect to v fb d v uvl = v fb ?v uvl 20 60 110 mv d v fb /v fb reference voltage line regulation v in = 2.65v to 6v (note 4) 0.05 0.25 %/v v loadreg output voltage load regulation measured in servo loop, v ith = 0.9v to 1.2v 0.1 0.6 % measured in servo loop, v ith = 1.6v to 1.2v 0.1 0.6 % v in input voltage range 2.65 6 v i q input dc bias current (note 5) pulse skipping mode 2.65v < v in < 6v, v sync/mode = 0v, i out = 0a 270 365 m a burst mode operation v sync/mode = v in , i out = 0a 15 22 m a shutdown v run = 0v, v in = 6v 0 1 m a f sync sync capture range 350 750 khz f osc oscillator frequency v fb 3 0.7v 495 550 605 khz v fb = 0v 80 khz i plllpf phase detector output current sinking capability f pllin < f osc 3 10 20 m a sourcing capability f pplin > f soc ? 10 20 m a r pfet r ds(on) of p-channel fet i sw = 100ma, v in = 5v 0.28 0.35 w r nfet r ds(on) of n-channel fet i sw = 100ma, v in = 5v 0.35 0.4 w i pk peak inductor current v fb = 0.7v, duty cycle < 35%, v in = 3v 1.6 2.15 2.75 a i lsw sw leakage v run = 0v, v sw = 0v or 6v, v in = 6v 0.01 2.5 m a v sync/mode sync/mode threshold 0.2 1.0 1.5 v i sync/mode sync/mode leakage current 0.01 1 m a (note 1) order part number LTC1875EGN t jmax = 125 c, q ja = 110 c/ w, q jc = 40 c/ w the denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v in = 3.6v unless otherwise noted. absolute m axi m u m ratings w ww u package/order i n for m atio n w u u electrical characteristics input supply voltage .................................. 0.3v to 7v i th , pll_lpf voltages ............................. 0.3v to 2.7v run/ss, v fb voltages ............................... 0.3v to v in sync/mode voltage ................................. 0.3v to v in (v pvin ?v swp ) voltage ............................... 0.3v to 7v v swn voltage .............................................. 0.3v to 7v p-channel switch source current (dc) .................... 2a n-channel switch sink current (dc) ........................ 2a peak switching sink and source current ................. 3a operating ambient temperature range (note 2) ............................................. 40 c to 85 c junction temperature (note 3, 6) ........................ 125 c storage temperature range ................ 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c top view gn package 16-lead plastic ssop 12 3 4 5 6 7 8 1615 14 13 12 11 10 9 sgnd run/ss v fb i th swp1 swn1 pgnd1 pv in1 pll_lpfsync/mode pgood sv in swp2swn2 pgnd2 pv in2 gn part marking 1875 consult ltc marketing for parts specified with wider operating temperature ranges. downloaded from: http:///
3 ltc1875 1875f v run run threshold v run ramping up 0.2 0.7 1.5 v i run run input current v run = 0v 0.01 1 m a symbol parameter conditions min typ max units the denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v in = 3.6v unless otherwise noted. electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired.note 2: the ltc1875e is guaranteed to meet specified performance from 0 c to 70 c. specifications over the 40 c to 85 c operating temperature range are assured by design, characterization and correlation withstatistical process controls. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: ltc1875: t j = t a + (p d ?110 c/w) note 4: the ltc1875 is tested in a feedback loop which servos v fb to the balance point for the error amplifier (v ith = 1.2v) note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency.note 6: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junctiontemperature will exceed 125 c when overtemperature protection is active. continuous operation above the specified maximum operating junctiontemperature may impair device reliability. temperature ( c) 50 25 0 25 50 75 100 125 r ds(on) ( ) 1875 g01 0.80.7 0.6 0.5 0.4 0.3 0.2 0.1 0 v in = 5v v in = 5v v in = 3v synchronous switchmain switch v in = 3v temperature ( c) 50 25 0 25 50 75 100 125 frequency (khz) 1875 g02 595575 555 535 515 495 v in = 3.6v supply voltage (v) 0 2 4 68 osc frequency (khz) 1875 g03 580570 560 550 540 530 r ds(on) vs temperature oscillator frequencyvs temperature oscillator frequencyvs supply voltage typical perfor a ce characteristics uw temperature ( c) ?0 0 50 100 125 supply current ( a) 1875 g04 300250 200 150 100 50 0 pulse skipping mode burst mode v in = 3.6v dc supply currentvs temperature input voltage (v) 02 4 6 8 r ds(on) ( ) 1875 g05 0.60.5 0.4 0.3 0.2 0.1 0 synchronous switch main switch temperature ( c) ?0 0 50 100 125 switch leakage ( a) 1875 g06 10 98 7 6 5 4 3 2 1 0 main switch synchronous switch v in = 7v run = 0v r ds(on) vs input voltage switch leakage currentvs temperature downloaded from: http:///
4 ltc1875 1875f typical perfor a ce characteristics uw load current (ma) 0 500 1000 1500 2000 output voltage (v) 1875 g07 1.841.82 1.80 1.78 1.76 1.74 1.72 1.70 burst mode operationv in = 3.6v l = 4.7 h output voltage vs load current load step (burst mode operation) v out 100mv/div i l 1a/div i th 1v/div 50 m s/div 1875 g08 v in = 3.6v c in = 22 m f v out = 1.5v c out = 47 m f l = 6.8 m hi load = 200ma to 1700ma temperature ( c) 50 25 0 25 50 75 100 125 reference voltage (mv) 1875 g13 805804 803 802 801 800 799 798 797 796 795 v in = 6v output current (ma) efficiency (%) 9590 85 80 75 70 65 60 55 50 0.1 10 100 1875 g14 1 1000 v in = 6v v in = 4.2v v in = 3v v in = 3.6v v out = 1.8v l = 4.7 h burst mode operation output current (ma) efficiency (%) 100 9080 70 60 50 40 30 20 10 0 0.1 10 100 1875 g15 1 1000 v in = 3.6v v out = 1.8v l = 4.7 h burst mode operationpulse skipping mode v in = 4.2v v in = 3.6v v in = 4.2v input voltage (v) efficiency (%) 100 9590 85 80 75 70 65 60 55 50 2 1875 g16 3 4 5 6 v out = 2.5v l = 6.8 h burst mode operation 100ma 1ma 0.1ma 10ma reference voltage vstemperature efficiency vs output current efficiency vs input voltage efficiency vs output current downloaded from: http:///
5 ltc1875 1875f load step response (pulseskipping mode) pulse skipping mode operation burst mode operation soft-start with shorted output typical perfor a ce characteristics uw i l 200ma/div v out 100mv/div sw 5v/div v out 100mv/div i l 1a/div i th 1v/div i l 200ma/div v out 100mv/div sw 5v/div i vin 500ma/div run/ss 1v/div 100 m s/div 1875 g09 v in = 3.6v c in = 22 m f v out = 1.5v c out = 47 m f l = 6.8 m hi load = 200ma to 1700ma 1 m s/div 1875 g10 v in = 4.2v c in = 22 m f v out = 2.5v c out = 47 m f l = 6.8 m hi load = 50ma 25 m s/div 1875 g11 v in = 4.2v c in = 22 m f v out = 2.5v c out = 47 m f l = 6.8 m hi load = 50ma 5ms/div 1875 g12 v in = 3.6v c in = 22 m f v out = 0v c out = 47 m f l = 6.8 m hi load = 0a downloaded from: http:///
6 ltc1875 1875f uu u pi fu ctio s sgnd (pin 1): signal ground pin. run/ss (pin 2): combination of soft-start and run control inputs. forcing this pin below 0.7v shuts down thedevice. in shutdown all functions are disabled and device draws zero supply current. for the proper operation of the part, force this pin above 2.5v. do not leave this pin floating. soft-start can be accomplished by raising the voltage on this pin gradually with an rc circuit. v fb (pin 3): feedback pin. receives the feedback voltage from an external resistor divider across the output.i th (pin 4): error amplifier compensation point. the current output increases with this control voltage. nomi-nal voltage range for this pin is 0.5v to 1.8v. swp1, swp2 (pins 5, 12): upper switch nodes. these pins connect to the drains of the internal main pmosswitches and should always be connected together externally. swn1, swn2 (pins 6, 11): lower switch nodes. these pins connect to the drains of the internal synchronousnmos switches and should always be connected together externally. pgnd1, pgnd2 (pins 7, 10): power ground pins. ground pins for the internal drivers and switches. these pinsshould always be tied together. pv in1 , pv in2 (pins 8, 9): power supply pins for the internal drivers and switches. these pins should alwaysbe tied together. sv in (pin 13): signal power supply pin. pgood (pin 14): power good indicator pin. power good is an open-drain logic output. the pgood pin is pulled toground when the voltage on the v fb pin is not within 7.5% of its nominally regulated potential. this pin re- quires a pull-up resistor for power good indication. powergood indication works in all modes of operation. sync/mode (pin 15): external clock synchronization and mode select input. to synchronize, apply an externalclock with a frequency between 350khz and 750khz. to select burst mode operation, tie pin to sv in . grounding this pin selects pulse skipping mode. do not leave this pinfloating. pll_lpf (pin 16): output of the phase detector and control input of oscillator. connect a series rc lowpassnetwork from this pin to ground if externally synchronized. if unused, this pin may be left open. downloaded from: http:///
7 ltc1875 1875f block diagra w + + + + + ea i th burst sleep en sleep 0.8v 0.86v 0.6v v fb sv in freq shift slope comp osc vco and osc x burst defeat y y = ??only when x is a constant ? run/ss sync/mode pll_lpf sr rs latch q 0.45v q switching logic and blanking circuit thermal shutdown anti- shoot- through ovdet ov + rcmp + 0.74v uvdet pgood shutdown sgnd soft-start 0.8v ref sv in + i comp 2.9 pgnd 7, 10 6, 11 8, 9 topmosfet bottommosfet 1875 fd swn pv in sv in 0.8v 14 1 4 1615 32 13 5, 12 swp downloaded from: http:///
8 ltc1875 1875f operatio u main control loopthe ltc1875 uses a constant frequency, current mode step-down architecture. both the top mosfet and syn- chronous bottom mosfet switches are internal. during normal operation, the internal top power mosfet is turned on each cycle when the oscillator sets the rs latch, and turned off when the current comparator, i comp , resets the rs latch. the peak inductor current at which i comp turns the top mosfet off is controlled by the voltage onthe i th pin, which is the output of error amplifier ea. when the load current increases, it causes a slight decrease inthe feedback voltage, v fb , relative to the 0.8v internal reference, which, in turn, causes the i th voltage to in- crease until the average inductor current matches the newload current. while the top mosfet is off, the bottom mosfet is turned on until either the inductor current starts to reverse direction or the next clock cycle begins. comparator ovdet guards against transient overshoots > 7.5% by turning the main switch off and keeping it off until the fault is removed. burst mode operation the ltc1875 is capable of burst mode operation in which the internal power mosfets operate intermittently based on load demand. to enable burst mode operation, simply tie the sync/mode pin to sv in or connect it to a logic high (v sync/mode > 1.5v). to disable burst mode operation and enable pwm pulse skipping mode, connect the sync/mode pin to sgnd. in this mode, the efficiency is lower at light loads but becomes comparable to burst mode opera- tion when the output load exceeds 100ma. the advantage of pulse skipping mode is lower output ripple. when the converter is in burst mode operation, the peak current of the inductor is set to approximately 400ma, even though the voltage at the i th pin indicates a lower value. the voltage at the i th pin drops when the inductor? average current is greater than the load requirement. as the i th voltage drops below approximately 0.45v, the burst comparator trips, turning off both power mosfets.the i th pin is then disconnected from the output of the ea amplifier and held 0.65v above ground.in sleep mode, both power mosfets are held off and the internal circuitry is partially turned off, reducing the quies- cent current to 15 m a. the load current is now being supplied from the output capacitor. when the outputvoltage drops, the i th pin reconnects to the output of the ea amplifier and the top mosfet is again turned on andthis process repeats. soft-start/run function the run/ss pin provides a soft-start function and a means to shut down the ltc1875. soft-start reduces the input current surge by gradually increasing the regulator? maximum output current. this pin can also be used for power supply sequencing. pulling the run/ss pin below 0.7v shuts down the ltc1875, which then draws < 1 m a current from the sup- ply. this pin can be driven directly from logic circuits asshown in figure 1. it is recommended that this pin is driven to v in during normal operation. note that there is no current flowing out of this pin. soft-start action is accom-plished by connecting an external rc network to the run/ ss pin as shown in figure 1. the ltc1875 actively pulls the run/ss pin to ground under low input supply voltage conditions. (refer to block diagram) 3.3v or 5v v in run/ss d1* 0.32v r ss c ss *zetex bat54 1875 f01 figure 1. run/ss pin interfacing downloaded from: http:///
9 ltc1875 1875f power good indicatorthe power good function monitors the output voltage in all modes of operation. its open-drain output is pulled low when the output voltage is not within 7.5% of its nomi- nally regulated voltage. the feedback voltage is filteredbefore it is fed to a power good window comparator in order to prevent false tripping of the power good signal during fast transients. the window comparator monitors the output voltage even in burst mode operation. in shutdown mode, open drain is actively pulled low to indicate that the output voltage is invalid. short-circuit protection when the output is shorted to ground, the frequency of the oscillator is reduced to about 80khz, 1/7 the nominal frequency. this frequency foldback ensures that the in- ductor current has more time to decay, thereby preventing runaway. the oscillator? frequency will progressively increase to 550khz (or to the synchronized frequency) when v fb rises above 0.3v. frequency synchronizationthe ltc1875 can be synchronized to an external clock source connected to the sync/mode pin. the turn-on of the top mosfet is synchronized to the rising edge of the external clock. when the ltc1875 is clocked by an external source, burst mode operation is disabled. in this synchronized mode, when the output load current is very low, current compara- tor, i comp , may remain tripped for several cycles and force the main switch to stay off for the same number of cycles.increasing the output load slightly allows constant fre- quency pwm operation to resume. frequency synchronization is inhibited when the feedback voltage v fb is below 0.6v. this prevents the external clock from interfering with the frequency foldback for short-circuit protection. low dropout operation when the input supply voltage decreases toward theoutput voltage in a buck regulator, the duty cycle in- creases toward the maximum on-time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the top mosfet and the inductor. low supply operationthe ltc1875 is designed to operate down to an input supply voltage of 2.65v although the maximum allowable output current is reduced at this low voltage. figure 2 shows the reduction in the maximum output current as a function of input voltage. another important detail to remember is that at low input supply voltages, the r ds(on) of the p-channel switch increases. therefore, the user should calculate the powerdissipation when the ltc1875 is used at 100% duty cycle with low supply voltage (see thermal considerations in the applications information section). input voltage (v) 2.5 0 max output current (ma) 500 1000 1500 2000 3.5 4.5 5.5 6.5 1875 f02 7.5 v out = 1.5v v out = 2.5v v out = 3.3v figure 2. maximum output current vs input voltage operatio u (refer to block diagram) downloaded from: http:///
10 ltc1875 1875f operatio u slope compensation and inductor peak currentslope compensation is required in order to prevent sub- harmonic oscillation at high duty cycles. it is accom- plished by internally adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. as a result, the maximum inductor peak current is reduced for duty cycles > 40%. this is shown in the decrease of the inductor peak current as a function of duty cycle graph in figure 3. figure 3. maximum inductor peak current vs duty cycle applicatio s i for atio wu uu the basic ltc1875 application circuit is shown on the firstpage of this data sheet. external component selection is driven by the load requirement and begins with the selec- tion of l followed by c in and c out . inductor value calculationthe inductor selection will depend on the operating fre- quency of the ltc1875. the internal nominal frequency is 550khz, but can be externally synchronized from 350khz to 750khz. the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. however, oper- ating at a higher frequency results in lower efficiency because of increased switching losses. the inductor value has a direct effect on ripple current. the ripple current d i l decreases with higher inductance or frequency and increases with higher input voltages. d= ()( ) ? ? ?? i fl v v v l out out in 1 1C (1) accepting larger values of d i l allows the use of smaller inductors, but results in higher output voltage ripple. a reasonable starting point for setting ripple current isd i l = 0.3(i max ). the inductor value also has an effect on burst modeoperation. the transition to low current operation begins when the inductor current peaks fall to approximately 500ma. lower inductor values (higher d i l ) will cause this to occur at lower load currents, which can cause a dip inefficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to increase. inductor selection the inductor should have a saturation current ratinggreater than the peak inductor current set by the current comparator of ltc1875. also, consideration should be given to the resistance of the inductor. inductor conduc- tion losses are directly proportional to the dc resistance of the inductor. manufacturers sometimes provide maxi- mum current ratings based on the allowable losses in theinductor. suitable inductors are available from coilcraft, coiltron-ics, dale, sumida, toko, murata, panasonic and other manufacturers. duty cycle (%) 0 maximum inductor peak current (ma) 22002000 1800 1600 1400 1200 1000 800 20 40 60 80 1875 f03 100 v in = 3v downloaded from: http:///
11 ltc1875 1875f c in and c out selection in continuous mode, the source current of the top mosfetis a trapezoidal waveform of duty cycle v out /v in . to prevent large voltage transients, a low esr input capacitorsized for the maximum rms current must be used. the maximum rms input capacitor current is given by: ii vvv v rms cin omax out in out in () / (C ) @ [] 12 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even significant devia-tions do not offer much relief. note that the capacitor manufacturer? ripple current ratings are often based on 2000 hours of life. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there are any questions. depending on how the ltc1875 circuit is powered up, you may need to check for input voltage transients. input voltage transients may be caused by input voltage steps or by connecting the circuit to an already powered up source such as a wall adapter. the sudden application of input voltage will cause a large surge of current in the input leads that will store energy in the parasitic induc- tance of the leads. this energy will cause the input voltage to swing above the dc level of the input power source and it may exceed the maximum voltage rating of the input capacitor and ltc1875. the easiest way to suppress input voltage transients is to add a small aluminum electrolytic capacitor in parallel with the low esr input capacitor. the selected capacitor needs to have the right amount of esr in order to critically dampen the resonant circuit formed by the input lead inductance and the input capacitor. the typical values of esr will fall in the range of 0.5 w to 2 w and capacitance will fall in the range of 5 m f to 50 m f. the selection of c out is driven by the required effective series resistance (esr). typically, once the esr require-ment is satisfied, the capacitance is adequate for filtering. the output ripple d v out is determined by: d@ d + ? ? ?? v i esr fc out l out 1 8 where f = operating frequency, c out = output capacitance and d i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since d i l increases with input voltage. for the ltc1875, the general rule forproper operation is: esr cout < 0.125 w the choice of using a smaller output capacitance in-creases the output ripple voltage due to the frequency dependent term but can be compensated for by using capacitor(s) of very low esr to maintain low ripple volt- age. the i th pin compensation components can be opti- mized to provide stable high performance transientresponse regardless of the output capacitor selected. manufacturers such as taiyo yuden, avx, kemet andsanyo should be considered for low esr, high perfor- mance capacitors. the poscap solid electrolytic chip capacitor available from sanyo is an excellent choice for output bulk capacitors due to its low esr/size ratio. once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. output voltage programmingthe output voltage is set by a resistor divider according to the following formula: vv r r out =+ ? ? ?? 08 1 1 2 . (2) the external resistor divider is connected to the output,allowing remote voltage sensing as shown in figure 4. applicatio s i for atio wu uu downloaded from: http:///
12 ltc1875 1875f applicatio s i for atio wu uu filter network on the pll_lpf pin. the relationship be-tween the voltage on the pll_lpf pin and operating frequency is shown in figure 5. a simplified block diagram is shown in figure 6. if the external frequency (v sync/mode ) is greater than 550khz, the center frequency, current is sourced continu-ously, pulling up the pll_lpf pin. when the external frequency is less than 550khz, current is sunk continu- ously, pulling down the pll_lpf pin. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. thus the voltage on the pll_lpf pin is adjusted until the phase and frequency of the external and internal oscillators are identical. at this stable operating point the phase com- parator output is open and the filter capacitor c lp holds the voltage.the loop filter components c lp and r lp smooth out the current pulses from the phase detector and provide astable input to the voltage controlled oscillator. the filter components c lp and r lp determine how fast the loop acquires lock. typically r lp = 10k and c lp is 2200pf to 0.01 m f. when not synchronized to an external clock, the internal connection to the vco is disconnected. thisdisallows setting the internal oscillation frequency by a dc voltage on the v plllpf pin. figure 5. relationship between oscillator frequencyand voltage at pll_lpf pin digital phase/ frequency detector sync/ mode pll_lpf 2.4v c lp 1875 f06 r lp vco figure 6. phase-locked loop block diagram phase-locked loop and frequency synchronizationthe ltc1875 has an internal voltage-controlled oscillator and phase detector comprising a phase-locked loop. this allows the mosfet turn-on to be locked to the rising edge of an external frequency source. the frequency range of the voltage-controlled oscillator is 350khz to 750khz. the phase detector used is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector will not lock up on input frequencies close to the harmonics of the vco center frequency. the pll hold-in range d f h is equal to the capture range, d f h = d f c = 200khz. the output of the phase detector is a pair of complemen-tary current sources charging or discharging the external v fb ltc1875 0.8v v out 6v sgnd r2 1875 f04 r1 figure 4. setting the ltc1875 output voltage v plllpf (v) 0 osc frequecny (khz) 1000 900800 700 600 500 400 300 200 100 0 1875 f05 0.5 1 1.5 2 downloaded from: http:///
13 ltc1875 1875f efficiency considerationsthe efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% ?(l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentageof input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in ltc1875 circuits: supply quiescent currents and i 2 r losses. the supply quiescent current loss dominates the efficiency loss at very low load current whereas the i 2 r loss dominates the efficiency loss at medium to high loadcurrents. in a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in figure 7. 1. the supply quiescent current is due to two compo-nents: the dc bias current as given in the electrical characteristics and the internal main switch and syn- chronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time thegate is switched from high to low to high again, a packet of charge dq moves from pv in to ground. the resulting dq/dt is the current out of pv in that is typically larger than the dc bias current. in continuous mode,i gatechg = f(q t + q b ) where q t and q b are the gate charges of the internal top and bottom switches. boththe dc bias and gate charge losses are proportional to supply voltage and thus their effects will be more pronounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches r sw and external inductor r l . in continuous mode the average output current flowingthrough inductor l is ?hopped?between the main switch and the synchronous switch. thus, the series resistance looking into sw pins is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) + r ds(on)bot )(1 ?dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteris-tics curves. thus, to obtain i 2 r losses, simply add r sw to r l and multiply by the square of the average output current. other losses including c in and c out esr dissipative losses, mosfet switching losses and inductor core lossesgenerally account for less than 2% total additional loss. thermal considerations in most applications, the ltc1875 does not dissipate much heat due to its high efficiency. but, in applications where the ltc1875 is running at high ambient tempera- ture with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction tempera- ture reaches approximately 150 c, both power switches will be turned off and the sw nodes will become highimpedance. applicatio s i for atio wu uu figure 7. power lost vs load current load current (ma) 0.001 power lost (w) 0.01 0.1 1 0.1 10 100 1000 1875 f07 0.0001 1 v in = 6v v out = 3.3v l = 6.8 h burst mode operation downloaded from: http:///
14 ltc1875 1875f to avoid the ltc1875 from exceeding the maximumjunction temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. normally, some iterative calculation is required to determine a rea- sonably accurate value. the temperature rise is given by: t r = p ? q ja where p is the power dissipated by the regulator and q ja is the thermal resistance from the junction of the die to theambient temperature. the junction temperature is given by: t j = t a + t r where t a is the ambient temperature. because the power transistor r ds(on) is a function of temperature, it is usually necessary to iterate 2 to 3 times through theequations to achieve a reasonably accurate value for the junction temperature. as an example, consider the ltc1875 in dropout at aninput voltage of 3v, a load current of 0.8a and an ambient temperature of 70 c. from the typical performance graph of switch resistance, the r ds(on) of the p-channel switch at 70 c is 0.35 w . therefore, power dissipated by the ic is: p = i 2 ?r ds(on) = 0.224w for the ssop package, the q ja is 110 c/w. thus the junction temperature of the regulator is: t j = 70 c + (0.224)(110) = 95 c however, at this temperature, the r ds(on) is actually 0.4 w . therefore: t j = 70 c + (0.256)(140) = 98 c which is below the maximum junction temperature of125 c. note that at higher supply voltages, the junction tempera-ture is lower due to reduced switch resistance (r ds(on) ). checking transient responsethe regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ( d i load ?esr), where esr is the effective series resistance of c out . d i load also begins to charge or discharge c out , generating a feedback error signal. the regulator loop then acts to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stabilityproblem. the i th pin can be used for external compensa- tion as shown in figure 9. (the capacitor, c c2 , is typically needed for noise decoupling.)a second, more severe transient is caused by switching in loads with large (> 1 m f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallelwith c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the loadswitch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 ?c load ). thus, a 10 m f capacitor charging to 3.3v would require a 250 m s rise time, limiting the charging current to about 130ma. applicatio s i for atio wu uu downloaded from: http:///
15 ltc1875 1875f dut r svin r pl pgnd v out v in c out c in2 c in1 l1 r pg c pl c c2 r c c c1 r fb2 r ss c ss r fb1 via connection to r fb1 via connection to v in vias to gnd plane vias to gnd plane 1875 f08 applicatio s i for atio wu uu pc board layout checklistas with all high frequency switchers, when considering layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. figure 8 is a sample of pc board layout for the design example shown in figure 9. a 4-layer pc board is used in this design. several guidelines are followed in this layout: 1. in order to minimize switching noise and improve output load regulation, the pgnd pins of the ltc1875should be connected directly to 1) the negative terminal of the output decoupling capacitors, 2) the negative terminal of the input capacitor and 3) vias to the ground plane immediately adjacent to pins 1, 7 and 10. the ground trace on the top layer of the pc board should be as wide and short as possible to minimize series resis- tance and inductance. 2. beware of ground loops in multiple layer pc boards. try to maintain one central ground node on the board anduse the input capacitor to avoid excess input ripple for high output current power supplies. if the ground is to be used for high dc currents, choose a path away from the small-signal components. 3. the high di/dt loop from the top terminal of the input capacitor, through the power mosfets and back to theinput capacitor should be kept as tight as possible to reduce inductive ringing. excess inductance can cause increased stress on the power mosfet and increase noise on the input. if low esr ceramic capacitors are used to reduce input noise, place these capacitors close to the dut in order to keep the series inductance to a minimum. figure 8. typical application and suggested layout (topside only) downloaded from: http:///
16 ltc1875 1875f applicatio s i for atio wu uu 4. place the small-signal components away from high frequency switching nodes. in the layout shown infigure 8, all of the small-signal components have been placed on one side of the ic and all of the power components have been placed on the other. 5. for optimum load regulation and true sensing, the top of the output resistor divider should connect indepen-dently to the top of the output capacitor (kelvin connec- tion), staying away from any high dv/dt traces. place the divider resistors near the ltc1875 in order to keep the high impedance fb node short. design exampleas a design example, assume the ltc1875 is used in a single lithium-ion battery-powered cellular phone applica- tion. the v in will be operating from a maximum of 4.2v down to about 2.65v. the load current requirement is amaximum of 1.5a but most of the time it will be on standby mode, requiring only 2ma. efficiency at both low and high load currents is important. output voltage is 2.5v. with this information we can calculate l using equation (1), l fi v v v l out out in = () d () ? ? ?? 1 1C (3) substituting v out = 2.5v, v in = 4.2v, d i l = 450ma and f = 550khz in equation (3) gives: l v khz ma vv h = ? ? ?? =m 25 550 450 1 2542 409 . ? C .. . a 4.7 m h inductor works well for this application. for good efficiency choose a 2a inductor with less than 0.125 w series resistance.c in will require an rms current rating of at least 0.75a at temperature and c out will require an esr of less than 0.125 w . in most applications, the requirements for these capacitors are fairly similar.for the feedback resistors, choose r2 = 412k. r1 can then be calculated from equation (2) to be: r v r k use k out 1 08 1 2 875 5 887 = ? ? ?? = . C ., figure 9 shows the complete circuit along with its effi-ciency curve. downloaded from: http:///
17 ltc1875 1875f 512 6 11 3 1 1875 f09a swpswp swnswn v fb i th r c 150k pll_lpf run/ss pgood sgnd 89 pv in pv in 710 pgndpgnd sync/mode r svin 10 ltc1875 l1 4.7 h v out * 2.5v/1.5a v in 2.65v to 4.2vgnd r1 887k r2412k c in1 10 f c out 47 f 15 13 14 2 16 4 sv in c svin 0.1 f c c1 47pf bold lines indicate high current paths c c2 220pf c in1 , c in2 : taiyo-yuden ceramic jmk316bj106ml c out : tdk ceramic c4532x5r0j476m l1: toko a921cy-4r7m*1.5a is the maximum output current r ss 1m power good r pg 100k c ss 0.1 f c in2 10 f figure 9a. single lithium-ion to 2.5v/1.5a regulator from design example applicatio s i for atio wu uu figure 9b. efficiency vs output current for design example output current (ma) efficiency (%) 100 9590 85 80 75 70 65 60 0.1 10 100 1875 f09b 1 1000 v in = 4.2v v in = 3v v out = 2.5v l = 4.7 h v in = 3.6v downloaded from: http:///
18 ltc1875 1875f 512 6 11 3 1 1875 ta02 swpswp swnswn v fb i th r c 150k pll_lpf run/ss pgood sgnd 89 pv in pv in 710 pgndpgnd sync/mode r svin 10 ltc1875 l1 4.7 h v out * 1.8v/1.5a v in 3v to 4.2v gnd c in1 10 f c out 47 f 15 13 14 2 16 4 sv in c svin 0.1 f c c1 47pf bold lines indicate high current paths c c2 220pf c in1 , c in2 : taiyo yuden ceramic jmk316bj106ml c out : tdk ceramic c4532x5r0j476m l1: toko a921cy-4r7m*1.5a is the maximum output current r ss 1m r pg 100k c ss 0.1 f power good c in2 10 f r1 523k r2412k typical applicatio u single li-ion to 1.8v/1.5a regulator using all ceramic capacitors efficiency vs output current ouput current (ma) efficiency (%) 100 9080 70 60 50 40 0.1 10 100 1875 ta02a 1 1000 v out = 1.8v l = 4.7 h v in = 4.2v v in = 3.3v downloaded from: http:///
19 ltc1875 1875f package descriptio n u gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. gn16 (ssop) 0502 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .053 ?.068 (1.351 ?1.727) .008 ?.012 (0.203 ?0.305) .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 typ .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note:1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale downloaded from: http:///
20 ltc1875 1875f ? linear technology corporation 2001 lt/tp 0403 2k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com 512 6 11 3 1 1875 ta03 swpswp swnswn v fb i th r c 150k pll_lpf run/ss pgood sgnd 89 pv in pv in 710 pgndpgnd sync/mode r svin 10 ltc1875 l1 4.7 h v out 3.3v*1a** v in 3v to 4.2v gnd c in1 10 f c out 47 f 15 13 14 2 16 4 sv in c svin 0.1 f power good c c1 47pf bold lines indicate high current paths c c2 220pf r ss 1m r pg 100k c ss 0.1 f c in2 10 f r1 1.29m r2412k c in1 , c in2 : taiyo yuden ceramic jmk316bj106ml c out : tdk ceramic c4532x5r0j476m l1: toko a921cy-4r7m*v out connected to v in for 3v < v in < 3.3v **1a is the maximum output current typical applicatio u single li-ion to 3.3v/1a regulator using all ceramic capacitors related parts part number description comments lt 1616 500ma (i out ), 1.4mhz high efficiency step-down 90% efficiency, v in : 3.6v to 25v, v out(min) : 1.25v, i q : 1.9ma, dc/dc converter i sd : <1 m a, thinsot tm lt1676 450ma (i out ), 100khz high efficiency step-down 90% efficiency, v in : 7.4v to 60v, v out(min) : 1.24v, i q : 3.2ma, dc/dc converter i sd : 2.5 m a, s8 lt1765 25v, 2.75a (i out ), 1.25mhz high efficiency step-down 90% efficiency, v in : 3v to 25v, v out(min) : 1.2v, i q : 1ma, dc/dc converter i sd : 15 m a, s8, tssop16e lt1776 500ma (i out ), 200khz high efficiency step-down 90% efficiency, v in : 7.4v to 40v, v out(min) : 1.24v, i q : 3.2ma, dc/dc converter i sd : 30 m a, n8, s8 ltc1878 600ma (i out ), 550khz synchronous step-down 95% efficiency, v in : 2.7v to 6v, v out(min) : 0.8v, i q : 10 m a, dc/dc converter i sd : <1 m a, ms8 ltc1879 1.2a (i out ), 550khz synchronous step-down dc/dc converter 95% efficiency, v in : 2.7v to 10v, v out(min) : 0.8v, i q : 15 m a, i sd : <1 m a, tssop16 lt1934/lt1934-1 300ma/70ma (i out ), high efficiency step-down v in : 3.2v to 34v, v out(min) : 1.2v, i q : 14 m a, i sd : <1 m a, thinsot dc/dc converters lt1940 dual output 1.4a (i out ) constant 1.1mhz, high efficiency v in : 3v to 25v, v out(min) : 1.2v, i q : 3.8ma, i sd : <1 m a, tssop16e step-down dc/dc converter ltc3405/ltc3405b 300ma (i out ), 1.5mhz synchronous step-down 95% efficiency, v in : 2.7v to 6v, v out(min) : 0.8v, i q : 20 m a, dc/dc converters i sd : <1 m a, thinsot ltc3406/ltc3406b 600ma (i out ), 1.5mhz synchronous step-down 95% efficiency, v in : 2.5v to 5.5v, v out(min) : 0.6v, i q : 20 m a, dc/dc converters i sd : <1 m a, thinsot ltc3411 1.25a (i out ), 4mhz synchronous step-down dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out(min) : 0.8v, i q : 60 m a, i sd : <1 m a, 10-lead ms ltc3412 2.5a (i out ), 4mhz synchronous step-down dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out(min) : 0.8v, i q : 60 m a, i sd : <1 m a, tssop16e ltc3430 60v, 2.75a (i out ), 200khz high efficiency step-down 90% efficiency, v in : 5.5v to 60v, v out(min) : 1.2v, i q : 2.5ma, dc/dc converter i sd : 25 m a, tssop16e ltc3440 600ma (i out ), 2mhz synchronous buck-boost 95% efficiency, v in : 2.5v to 5.5v, v out(min) : 2.5v, i q : 25 m a, dc/dc converter i sd : <1 m a, 10-lead ms thinsot is a trademark of linear technology corporation. downloaded from: http:///

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